1. Field of the Disclosure
The present disclosure generally relates to synchronous circuits and, more particularly, to synchronous capturing of outputs of signal paths of integrated circuits.
2. Description of the Related Art
Integrated circuits often employ synchronous digital signal paths. Typically, the synchronization of such paths is achieved through the use of clocked flip-flops that capture the output signal of a corresponding signal path responsive to an edge or state of a clock signal. However, different signal paths may exhibit different degrees of path delay depending on the voltage level at which the circuitry is operated. Those signal paths for which the signal propagation delay is primarily due to transistor gate delays (“gate-dominated signal paths”) often limit the maximum clocking frequency at lower voltages, whereas those signal paths for which the signal propagation delay is primarily due to resistor-capacitor (RC) effects (“RC-dominated signal paths”) tend to have signal propagation delays that do not materially scale with voltage. As such, gate-dominated signal paths tend to speed up with increases in operating voltage, whereas RC-dominated signal paths largely stay the same. Accordingly, the signal paths for the integrated circuit typically are configured so as to achieve a relative maximum frequency suitable for both low voltage operation and high voltage operation, which typically results in the signal paths being less than ideal for any one mode of operation.
The use of the same reference symbols in different drawings indicates similar or identical items.